In the manufacture of next generation integrated circuits, the fabrication of gate electrodes for complementary metal-oxide-semiconductor (CMOS) transistors has advanced to replace silicon dioxide and polysilicon with high-k dielectric materials and metal. A replacement metal gate process is often used to form the gate electrode. A typical replacement metal gate process begins by forming a high-k dielectric material and a sacrificial gate between a pair of spacers on a semiconductor substrate. After further processing steps, such as an annealing process, the sacrificial gate is removed and the resulting trench is filled with one or more metal layers. The metal layers can include workfunction metals as well as polysilicon electrode layers. This type of MOS transistor is often referred to as a high-k/metal gate transistor.
One conventional process flow for forming a gate stack for a high-k/metal gate transistor begins by depositing a high-k dielectric layer, a workfunction metal layer, a barrier layer, and a polysilicon layer on a semiconductor substrate. These layers are patterned to form a gate stack and then spacers are deposited and etched. An interlayer dielectric may then be deposited and planarized atop the gate stack and substrate.
It is highly desirable to remove the polysilicon layer and replace it with a metal layer to improve performance and decrease resistance within the gate stack. Unfortunately, after the polysilicon layer is removed from the gate stack, conventional metal deposition processes cannot easily deposit metal into the trench that is left behind. For instance, as CMOS transistor dimensions decrease, issues such as trench overhang and void formation become more challenging and more rampant. This is because at smaller dimensions, the aspect ratio of the trench between the spacers where the metal gate electrode is deposited becomes very aggressive. Accordingly, known processes cannot be used to replace the polysilicon layer with a metal layer.